1. Field of the Invention
The present invention relates to a method and system for interfacing computer processors. In particular, the present invention relates to a computer system interface that provides for the integration of reconfigurable processors with instruction processors and other reconfigurable processors.
2. Discussion of the Related Art
Typical computing systems generally include traditional instruction processors for processing and controlling the instructions and data flow of a typical computer program. Computer instructions can also be implemented with hardware logic. Hardware logic-implemented functions can greatly accelerate the processing of application algorithms over those same algorithms implemented in software. Sections of code such as compute-intensive algorithms, and/or repetitious instructions can benefit from hardware implementation. Although computer instructions implemented in hardware logic run much faster than those implemented in software, hardware logic is much more expensive to design, develop, and manufacture than an average computer application.
Recently reconfigurable processors have been added to computer systems, allowing for the processing of computer software, as well as providing for the hardware implementation of a computer program or code segments. Any piece of code deemed suitable for hardware performance can be segregated from an application program and processed by one or more reconfigurable processors. The remaining code, the code not converted for hardware implementation, is simply processed by the standard instruction processors.
In such hybrid computer systems the computer code is divided into sections, generally during compilation. Depending on optimization requirements these sections of code can then be processed by one or more instruction processors, and/or one or more reconfigurable processors.
Performance enhancements resulting from reconfigurable computing can provide orders of magnitude improvements in speed for a wide variety of computing code. However, the coordination between the instruction processors, reconfigurable processors, main memory, and various other components can degrade these performance improvements. Additionally, the increased number of components necessary to coordinate such a hybrid computer system can add significantly to the overall cost.